1. Field of the Invention
The present invention relates to a semiconductor memory device such as a ferroelectric random access memory (FeRAM) device, and more particularly, to the improvement of a reliability test or a burn-in test of the semiconductor memory device.
2. Description of the Related Art
In a prior art semiconductor memory device including a plurality of word lines, a plurality of pairs of bit lines, a plurality of memory cells each connected between one of the word lines and one of the bit lines, and a plurality of sense amplifiers for amplifying the difference in potential between the pair of the bit line a plurality of offset circuits is provided for applying an offset voltage to at least one of the pair of the bit lines to reduce the difference in potential between the pair of the bit lines before the sense amplifiers are operated, thus carrying out a reliability test, i.e., a burn-in test (see: JP-A-11-149796). This will be explained later in detail.
In the above-described prior art semiconductor memory device, however, the offset voltage is greatly dependent upon the voltage at a bit line. As a result, if the offset voltage is too large, some of normal semiconductor memory devices will be deemed to be defective and scrapped. On the other hand, if the offset voltage is too small, some of defective semiconductor memory devices will pass. Thus, it is impossible to carry out a high reliability test.